SHARC+ Core infrastructure
400MHz (max) Core clock frequency
640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance
32-bit, 40-bit & 64-bit floating point support
32-bit fixed point
Byte, short-word, word, long-word addressed

Memory
256KB on-chip Level 2 (L2) SRAM with ECC protection – eliminates need for external memory in many use cases
One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices

16-bit DDR/DDR3L Memory Controller
1.35V support for DDR3L

Advanced Hardware Accelerators
Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power
Security Crypto Engines with OTP

Powerful DMA System

Innovative Digital Audio Interface (DAI) includes:
8x Full SPORT interfaces w/TDM & I2S modes
2x S/PDIF Rx/Tx, 8 ASRC pairs
4x Precision Clock Generators
28 Buffers

Other Peripheral Connectivity / Interfaces:
2x Quad SPI, 1x Octal SPI
MLB 3-pin
6x I2C,3x UARTs
2x Link Ports
10x General Purpose Timer, 1x General Purpose Counter
2x Watchdog Timers
4-ch 12bit Housekeeping ADCs
40 GPIO pins, 28 DAI pins
Thermal Sensor

17mm x 17mm (0.8mm pitch) 400-ball CSP_BGA

Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1 GHz
AEC-Q100 qualified for automotive applications

Type : 16-bit
Applications : general purpose, for automotive applications
Other characteristics : analog